Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2086221
date_generatedThu Apr 5 14:11:50 2018 os_platformWIN64
product_versionVivado v2017.4 (64-bit) project_idd09cbe1609ce4ccd852b2bcaef909534
project_iteration3 random_ida91cfa5951b1516890b4fa4e8ef059db
registration_id176233316_1777497009_210621211_364 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6700 CPU @ 3.40GHz cpu_speed3408 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
applyrsbmultiautomationdialog_checkbox_tree=1 basedialog_apply=1 basedialog_cancel=2 basedialog_ok=25
boardtreepanel_board_tree_panel=4 configurebitstreamdialog_toc_list=7 coretreetablepanel_core_tree_table=4 createconstraintsfilepanel_file_name=1
filesetpanel_file_set_panel_tree=5 flownavigatortreepanel_flow_navigator_tree=19 gettingstartedview_create_new_project=1 mainmenumgr_export=6
mainmenumgr_file=14 mainmenumgr_floorplanning=1 mainmenumgr_import=4 mainmenumgr_report=2
mainmenumgr_timing=1 mainmenumgr_tools=6 newexporthardwaredialog_include_bitstream=1 pacommandnames_config_bitstream=2
pacommandnames_create_top_hdl=2 pacommandnames_disconnect_rsb_pin=1 pacommandnames_export_hardware=3 pacommandnames_launch_hardware=3
pacommandnames_regenerate_layout=2 pacommandnames_validate_rsb_design=1 partchooser_boards=10 projectnamechooser_project_name=1
projecttab_close_design=1 rdicommands_delete=1 removesourcesdialog_also_delete=1 rsbapplyautomationbar_run_block_automation=1
rsbapplyautomationbar_run_connection_automation=1 saveprojectutils_save=1 settingsdialog_project_tree=1 systembuilderview_add_ip=1
java_command_handlers
autoconnectboardcomp=4 configurebitstream=2 createblockdesign=1 createtophdl=2
customizersbblock=1 disconnectrsbpin=1 editdelete=1 newexporthardware=3
newlaunchhardware=3 newproject=1 regeneratersblayout=2 runbitgen=5
runimplementation=2 toolssettings=6 validatersbdesign=1 viewtaskimplementation=2
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=15 totalsynthesisruns=15

unisim_transformation
post_unisim_transformation
and2b1l=4 bscane2=1 bufg=4 carry4=76
fdce=338 fdpe=59 fdre=6161 fdse=297
gnd=583 ibuf=16 lut1=207 lut2=825
lut3=988 lut4=1591 lut5=1139 lut6=1841
mmcme2_adv=1 muxf7=252 muxf8=68 obuf=23
obuft=13 ramb36e1=18 ramd32=1400 rams32=440
srl16e=197 srlc16e=8 srlc32e=477 startupe2=1
vcc=513
pre_unisim_transformation
and2b1l=4 bscane2=1 bufg=4 carry4=76
fdce=338 fdpe=59 fdre=6161 fdse=297
gnd=583 ibuf=3 iobuf=13 lut1=207
lut2=825 lut3=988 lut4=1591 lut5=1075
lut6=1777 lut6_2=64 mmcme2_adv=1 muxf7=252
muxf8=68 obuf=23 ram32m=220 ram32x1d=40
ramb36e1=18 srl16e=197 srlc16e=8 srlc32e=477
startupe2=1 vcc=513

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=8 bram_ports_total=36 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=4903 srls_augmented=0
srls_newly_gated=0 srls_total=586

ip_statistics
IP_Integrator/1
bdsource=SBD core_container=NA iptotal=1 maxhierdepth=1
numblks=37 numhdlrefblks=0 numhierblks=8 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=29 numsysgenblks=0
synth_mode=Global x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=bd_afc3
x_ipvendor=xilinx.com x_ipversion=1.00.a
IP_Integrator/2
bdsource=USER core_container=NA da_axi4_cnt=3 da_board_cnt=2
da_clkrst_cnt=2 da_mb_cnt=1 iptotal=1 maxhierdepth=1
numblks=19 numhdlrefblks=0 numhierblks=5 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=14 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=design_1
x_ipvendor=xilinx.com x_ipversion=1.00.a
MDM/1
c_avoid_primitives=0 c_bscanid=76547328 c_data_size=32 c_dbg_mem_access=0
c_dbg_reg_access=0 c_debug_interface=0 c_ext_trig_reset_value=0xF1234 c_family=artix7
c_interconnect=2 c_jtag_chain=2 c_m_axi_addr_width=32 c_m_axi_data_width=32
c_m_axi_thread_id_width=1 c_m_axis_data_width=32 c_m_axis_id_width=7 c_mb_dbg_ports=1
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_trace_async_reset=0
c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90 c_trace_data_width=32 c_trace_id=110
c_trace_output=0 c_trace_protocol=1 c_use_bscan=0 c_use_config_reset=0
c_use_cross_trigger=0 c_use_uart=0 core_container=NA iptotal=1
x_ipcorerevision=12 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=mdm
x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.2
MicroBlaze/1
c_addr_tag_bits=11 c_allow_dcache_wr=1 c_allow_icache_wr=1 c_area_optimized=0
c_async_interrupt=1 c_async_wakeup=3 c_avoid_primitives=0 c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 c_cache_byte_size=16384 c_d_axi=1 c_d_lmb=1
c_daddr_size=32 c_data_size=32 c_dcache_addr_tag=11 c_dcache_always_used=1
c_dcache_baseaddr=0x0000000060000000 c_dcache_byte_size=16384 c_dcache_data_width=0 c_dcache_force_tag_lutram=0
c_dcache_highaddr=0x0000000061ffffff c_dcache_line_len=4 c_dcache_use_writeback=0 c_dcache_victims=0
c_debug_counter_width=32 c_debug_enabled=1 c_debug_event_counters=5 c_debug_external_trace=0
c_debug_interface=0 c_debug_latency_counters=1 c_debug_profile_size=0 c_debug_trace_async_reset=0
c_debug_trace_size=8192 c_div_zero_exception=0 c_dynamic_bus_sizing=0 c_ecc_use_ce_exception=0
c_edge_is_positive=1 c_endianness=1 c_family=artix7 c_fault_tolerant=0
c_fpu_exception=0 c_freq=100000000 c_fsl_exception=0 c_fsl_links=0
c_i_axi=0 c_i_lmb=1 c_iaddr_size=32 c_icache_always_used=1
c_icache_baseaddr=0x0000000060000000 c_icache_data_width=0 c_icache_force_tag_lutram=0 c_icache_highaddr=0x0000000061ffffff
c_icache_line_len=4 c_icache_streams=0 c_icache_victims=0 c_ill_opcode_exception=0
c_imprecise_exceptions=0 c_instance=design_1_microblaze_0_0 c_instr_size=32 c_interconnect=2
c_interrupt_is_edge=0 c_lockstep_master=0 c_lockstep_slave=0 c_m0_axis_data_width=32
c_m10_axis_data_width=32 c_m11_axis_data_width=32 c_m12_axis_data_width=32 c_m13_axis_data_width=32
c_m14_axis_data_width=32 c_m15_axis_data_width=32 c_m1_axis_data_width=32 c_m2_axis_data_width=32
c_m3_axis_data_width=32 c_m4_axis_data_width=32 c_m5_axis_data_width=32 c_m6_axis_data_width=32
c_m7_axis_data_width=32 c_m8_axis_data_width=32 c_m9_axis_data_width=32 c_m_axi_d_bus_exception=0
c_m_axi_dc_addr_width=32 c_m_axi_dc_aruser_width=5 c_m_axi_dc_awuser_width=5 c_m_axi_dc_buser_width=1
c_m_axi_dc_data_width=32 c_m_axi_dc_exclusive_access=0 c_m_axi_dc_ruser_width=1 c_m_axi_dc_thread_id_width=1
c_m_axi_dc_user_value=31 c_m_axi_dc_wuser_width=1 c_m_axi_dp_addr_width=32 c_m_axi_dp_data_width=32
c_m_axi_dp_exclusive_access=0 c_m_axi_dp_thread_id_width=1 c_m_axi_i_bus_exception=0 c_m_axi_ic_addr_width=32
c_m_axi_ic_aruser_width=5 c_m_axi_ic_awuser_width=5 c_m_axi_ic_buser_width=1 c_m_axi_ic_data_width=32
c_m_axi_ic_ruser_width=1 c_m_axi_ic_thread_id_width=1 c_m_axi_ic_user_value=31 c_m_axi_ic_wuser_width=1
c_m_axi_ip_addr_width=32 c_m_axi_ip_data_width=32 c_m_axi_ip_thread_id_width=1 c_mmu_dtlb_size=4
c_mmu_itlb_size=2 c_mmu_privileged_instr=0 c_mmu_tlb_access=3 c_mmu_zones=16
c_num_sync_ff_clk=2 c_num_sync_ff_clk_debug=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_dbg_clk=1
c_num_sync_ff_dbg_trace_clk=2 c_number_of_pc_brk=1 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0
c_opcode_0x0_illegal=0 c_optimization=0 c_pc_width=32 c_piaddr_size=32
c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000 c_reset_msr=0x00000000
c_s0_axis_data_width=32 c_s10_axis_data_width=32 c_s11_axis_data_width=32 c_s12_axis_data_width=32
c_s13_axis_data_width=32 c_s14_axis_data_width=32 c_s15_axis_data_width=32 c_s1_axis_data_width=32
c_s2_axis_data_width=32 c_s3_axis_data_width=32 c_s4_axis_data_width=32 c_s5_axis_data_width=32
c_s6_axis_data_width=32 c_s7_axis_data_width=32 c_s8_axis_data_width=32 c_s9_axis_data_width=32
c_sco=0 c_unaligned_exceptions=0 c_use_barrel=0 c_use_branch_target_cache=0
c_use_config_reset=0 c_use_dcache=1 c_use_div=0 c_use_ext_brk=0
c_use_ext_nm_brk=0 c_use_extended_fsl_instr=0 c_use_fpu=0 c_use_hw_mul=0
c_use_icache=1 c_use_interrupt=0 c_use_mmu=0 c_use_msr_instr=0
c_use_non_secure=0 c_use_pcmp_instr=0 c_use_reorder_instr=1 c_use_stack_protection=0
core_container=NA iptotal=1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=microblaze x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=10.0
axi_crossbar_v2_1_16_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=artix7
c_m_axi_addr_width=0x0000001000000010 c_m_axi_base_addr=0x00000000406000000000000044a00000 c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_read_issuing=0x0000000100000001
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_write_issuing=0x0000000100000001 c_num_addr_ranges=1
c_num_master_slots=2 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=16
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2017.4
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_emc/1
c_axi_clk_period_ps=10000 c_family=artix7 c_include_datawidth_matching_0=1 c_include_datawidth_matching_1=1
c_include_datawidth_matching_2=1 c_include_datawidth_matching_3=1 c_include_negedge_ioregs=0 c_instance=axi_emc_inst
c_lflash_period_ps=10000 c_linear_flash_sync_burst=0 c_max_mem_width=8 c_mem0_type=1
c_mem0_width=8 c_mem1_type=0 c_mem1_width=16 c_mem2_type=0
c_mem2_width=16 c_mem3_type=0 c_mem3_width=16 c_mem_a_lsb=0
c_mem_a_msb=31 c_num_banks_mem=1 c_page_size=16 c_parity_type_mem_0=0
c_parity_type_mem_1=0 c_parity_type_mem_2=0 c_parity_type_mem_3=0 c_port_diff=0
c_s_axi_en_reg=0 c_s_axi_mem0_baseaddr=0x60000000 c_s_axi_mem0_highaddr=0x61FFFFFF c_s_axi_mem1_baseaddr=0xB0000000
c_s_axi_mem1_highaddr=0xBFFFFFFF c_s_axi_mem2_baseaddr=0xC0000000 c_s_axi_mem2_highaddr=0xCFFFFFFF c_s_axi_mem3_baseaddr=0xD0000000
c_s_axi_mem3_highaddr=0xDFFFFFFF c_s_axi_mem_addr_width=32 c_s_axi_mem_data_width=32 c_s_axi_mem_id_width=1
c_s_axi_reg_addr_width=5 c_s_axi_reg_data_width=32 c_synch_pipedelay_0=1 c_synch_pipedelay_1=1
c_synch_pipedelay_2=1 c_synch_pipedelay_3=1 c_tavdv_ps_mem_0=8000 c_tavdv_ps_mem_1=15000
c_tavdv_ps_mem_2=15000 c_tavdv_ps_mem_3=15000 c_tcedv_ps_mem_0=8000 c_tcedv_ps_mem_1=15000
c_tcedv_ps_mem_2=15000 c_tcedv_ps_mem_3=15000 c_thzce_ps_mem_0=8000 c_thzce_ps_mem_1=7000
c_thzce_ps_mem_2=7000 c_thzce_ps_mem_3=7000 c_thzoe_ps_mem_0=8000 c_thzoe_ps_mem_1=7000
c_thzoe_ps_mem_2=7000 c_thzoe_ps_mem_3=7000 c_tlzwe_ps_mem_0=3000 c_tlzwe_ps_mem_1=0
c_tlzwe_ps_mem_2=0 c_tlzwe_ps_mem_3=0 c_tpacc_ps_flash_0=25000 c_tpacc_ps_flash_1=25000
c_tpacc_ps_flash_2=25000 c_tpacc_ps_flash_3=25000 c_twc_ps_mem_0=8000 c_twc_ps_mem_1=15000
c_twc_ps_mem_2=15000 c_twc_ps_mem_3=15000 c_twp_ps_mem_0=8000 c_twp_ps_mem_1=12000
c_twp_ps_mem_2=12000 c_twp_ps_mem_3=12000 c_twph_ps_mem_0=12000 c_twph_ps_mem_1=12000
c_twph_ps_mem_2=12000 c_twph_ps_mem_3=12000 c_use_startup=0 c_wr_rec_time_mem_0=27000
c_wr_rec_time_mem_1=27000 c_wr_rec_time_mem_2=27000 c_wr_rec_time_mem_3=27000 core_container=NA
iptotal=1 x_ipcorerevision=15 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_emc x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=3.0
axi_quad_spi/1
async_clk=1 c_dual_quad_mode=0 c_family=artix7 c_fifo_depth=16
c_instance=axi_quad_spi_inst c_lsb_stup=0 c_num_ss_bits=1 c_num_transfer_bits=8
c_s_axi4_addr_width=24 c_s_axi4_baseaddr=0xFFFFFFFF c_s_axi4_data_width=32 c_s_axi4_highaddr=0x00000000
c_s_axi4_id_width=1 c_s_axi_addr_width=7 c_s_axi_data_width=32 c_sck_ratio=2
c_select_xpm=0 c_shared_startup=0 c_spi_mem_addr_bits=24 c_spi_memory=2
c_spi_mode=2 c_sub_family=artix7 c_type_of_axi4_interface=0 c_uc_family=0
c_use_startup=1 c_use_startup_ext=0 c_xip_mode=0 core_container=NA
iptotal=1 x_ipcorerevision=14 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_quad_spi x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=3.2
axi_uartlite/1
c_baudrate=9600 c_data_bits=8 c_family=artix7 c_odd_parity=0
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=19 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
bd_afc3/1
advanced_properties=0 component_name=design_1_axi_smc_0 core_container=NA has_aresetn=1
iptotal=1 num_clks=1 num_mi=1 num_si=2
x_ipcorerevision=7 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=smartconnect
x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
blk_mem_gen_v8_4_1/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=8 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=1
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 20.388 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=design_1_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=8192 c_read_depth_b=8192 c_read_width_a=32 c_read_width_b=32
c_rst_priority_a=CE c_rst_priority_b=CE c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_bram_block=1 c_use_byte_wea=1 c_use_byte_web=1
c_use_default_data=0 c_use_ecc=0 c_use_softecc=0 c_use_uram=0
c_wea_width=4 c_web_width=4 c_write_depth_a=8192 c_write_depth_b=8192
c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=32 c_write_width_b=32
c_xdevicefamily=artix7 core_container=false iptotal=1 x_ipcorerevision=1
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=blk_mem_gen x_ipproduct=Vivado 2017.4
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=8.4
clk_wiz_v5_4_3_0/1
clkin1_period=83.333 clkin2_period=10.0 clock_mgr_type=NA component_name=design_1_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000007FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_mask=0x0000000040000000 c_mask1=0x0000000000800000
c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1 c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2 core_container=NA
iptotal=1 x_ipcorerevision=14 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2017.4 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=4.0
lmb_bram_if_cntlr/2
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
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read_latency_a=2 read_latency_b=0 read_reset_value_a=0 read_reset_value_b=0
use_embedded_constraint=0 use_mem_init=0 version=0 wakeup_time=0
write_data_width_a=70 write_data_width_b=70 write_mode_a=1 write_mode_b=1
xpm_memory_sdpram/1
write_mode_b=1 addr_width_a=5 addr_width_b=5 auto_sleep_time=0
byte_write_width_a=70 clocking_mode=0 core_container=NA ecc_mode=0
iptotal=14 memory_optimization=true memory_primitive=1 memory_size=2240
message_control=0 p_clocking_mode=0 p_ecc_mode=0 p_memory_optimization=1
p_memory_primitive=1 p_wakeup_time=0 p_write_mode_b=1 read_data_width_b=70
read_latency_b=0 read_reset_value_b=0 use_embedded_constraint=0 use_mem_init=0
wakeup_time=0 write_data_width_a=70 write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
bufc-1=1 cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=4 bufgctrl_util_percentage=12.50
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=18 block_ram_tile_util_percentage=36.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=18 ramb36_fifo_util_percentage=36.00
ramb36e1_only_used=18
primitives
and2b1l_functional_category=Others and2b1l_used=4 bscane2_functional_category=Others bscane2_used=1
bufg_functional_category=Clock bufg_used=4 carry4_functional_category=CarryLogic carry4_used=76
fdce_functional_category=Flop & Latch fdce_used=333 fdpe_functional_category=Flop & Latch fdpe_used=58
fdre_functional_category=Flop & Latch fdre_used=4235 fdse_functional_category=Flop & Latch fdse_used=277
ibuf_functional_category=IO ibuf_used=16 lut1_functional_category=LUT lut1_used=134
lut2_functional_category=LUT lut2_used=676 lut3_functional_category=LUT lut3_used=861
lut4_functional_category=LUT lut4_used=1135 lut5_functional_category=LUT lut5_used=1109
lut6_functional_category=LUT lut6_used=1550 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=252 muxf8_functional_category=MuxFx muxf8_used=68
obuf_functional_category=IO obuf_used=23 obuft_functional_category=IO obuft_used=13
ramb36e1_functional_category=Block Memory ramb36e1_used=18 ramd32_functional_category=Distributed Memory ramd32_used=594
rams32_functional_category=Distributed Memory rams32_used=176 srl16e_functional_category=Distributed Memory srl16e_used=188
srlc16e_functional_category=Distributed Memory srlc16e_used=7 srlc32e_functional_category=Distributed Memory srlc32e_used=391
startupe2_functional_category=Others startupe2_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=252 f7_muxes_util_percentage=1.55
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=68 f8_muxes_util_percentage=0.83
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=386 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=4661 lut_as_logic_util_percentage=22.41 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=901 lut_as_memory_util_percentage=9.39 lut_as_shift_register_fixed=0 lut_as_shift_register_used=515
register_as_and_or_available=41600 register_as_and_or_fixed=0 register_as_and_or_used=4 register_as_and_or_util_percentage=<0.01
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=4853 register_as_flip_flop_util_percentage=11.67
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=5562 slice_luts_util_percentage=26.74
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=4857 slice_registers_util_percentage=11.68
fully_used_lut_ff_pairs_fixed=11.68 fully_used_lut_ff_pairs_used=272 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=386
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=4661 lut_as_logic_util_percentage=22.41
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=901 lut_as_memory_util_percentage=9.39
lut_as_shift_register_fixed=0 lut_as_shift_register_used=515 lut_ff_pairs_with_one_unused_flip_flop_fixed=515 lut_ff_pairs_with_one_unused_flip_flop_used=1960
lut_ff_pairs_with_one_unused_lut_output_fixed=1960 lut_ff_pairs_with_one_unused_lut_output_used=1971 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=2440 lut_flip_flop_pairs_util_percentage=11.73 slice_available=8150 slice_fixed=0
slice_used=2027 slice_util_percentage=24.87 slicel_fixed=0 slicel_used=1328
slicem_fixed=0 slicem_used=699 unique_control_sets_used=315 using_o5_and_o6_fixed=315
using_o5_and_o6_used=71 using_o5_output_only_fixed=71 using_o5_output_only_used=10 using_o6_output_only_fixed=10
using_o6_output_only_used=434
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=1 startupe2_util_percentage=100.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=10174587 bogomips=0 bram18=0 bram36=18
bufg=0 bufr=0 congestion_level=0 ctrls=315
dsp=0 effort=2 estimated_expansions=7851756 ff=4907
global_clocks=4 high_fanout_nets=2 iob=39 lut=6088
movable_instances=13167 nets=28736 pins=76669 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:36s hls_ip=0 memory_gain=486.832MB memory_peak=832.367MB